Clock synchronization scheme for deskewing operations in a data interface

ABSTRACT

A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

BACKGROUND

The invention generally relates to a clock synchronization scheme fordeskewing operations in a data interface, such an interface to a memorybus, for example.

A typical memory controller hub, or north bridge, of a computer systemincludes a memory interface, which establishes communication between thememory controller hub and the memory bus. The memory bus typically skewsthe data bit signals with respect to the clock signal. Therefore, thememory interface typically implements a scheme to adjust the timingbetween the data bit and clock signals to compensate for the skewing. Inconventional de-skewing schemes, the timing may be adjusted on all ofthe outgoing data bit signals as a group by adjusting read pointers thatpoint to the data bits in output buffers.

More specifically, a conventional memory interface of a memorycontroller hub may have a core partition, which furnishes the data thatis to be written to the memory. An analog partition of the memoryinterface generates the clock and data signals that appear on the memorybus; and a high speed input/output (HSIO) partition contains first infirst out (FIFO) circuits to handle the clock domain transfer betweenthe core and analog partitions.

A conventional memory interface may delay the clock signal that is sentto the analog I/O partition for purposes of optimizing the channeltiming, and after the I/O clock setting is fixed by channelrequirements, the I/O partition clock signal triggers the read pointersfor all of the FIFOs of the HSIO partition. The FIFOs must be deepenough to absorb the variation differences between the I/O clock treeand the clock signal provided by the core partition. The deeper the FIFOis, the larger the latency and the power dissipation will be. However,such a design may require the FIFOs to be too large to be incorporatedinto the analog I/O interface. Furthermore, conventional de-skewingschemes do not allow compensation for the individual data bit lines, asthe timing is regulated for the data bit lines as a group.

Thus, there is a continuing need for better ways to implement de-skewingin a data, such as a memory interface.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a schematic diagram of a memory subsystem according to anembodiment of the invention.

FIG. 2 is a schematic diagram of a memory interface of the memorysubsystem of FIG. 1 according to an embodiment of the invention.

FIG. 3 is a flow diagram depicting a clock de-skewing techniqueaccording to an embodiment of the invention.

DETAILED DESCRIPTION

Referring to FIG. 1, an embodiment 10 of a memory subsystem inaccordance with the invention includes a north bridge, or memorycontroller hub (MCH) 20, which generally serves as an interface forcomponents of a computer system (not shown) for purposes of storing datain and retrieving data from a memory 30 (a dynamic random access memory(DRAM), for example). In this regard, the MCH 20 may communicate withthe memory 30 via a memory bus 24. For this purpose, the MCH 20 mayinclude core logic 22, which as its name implies, generates data to betransmitted to the memory 30 through a memory interface 23. As describedherein, the memory interface 23 de-skews the data and clock signals thatare provided to the memory bus 24 (i.e., time-shifts the data signals sothat the data signals are appropriately aligned with the clock signals);and the memory interface 23 implements a clock synchronization scheme inconnection with the de-skewing operations for purposes of improving therate at which data is communicated through the memory interface 23. Asalso described herein, the memory interface 23 de-skews the data bitsignals on an individual basis and at the same time globally adjusts thetiming of the data bit signals to account for such global factors asvoltage and temperature drift.

Referring to FIG. 2 in conjunction with FIG. 1, in accordance with someembodiments of the invention, the memory interface 23 includes highspeed input/output (HSIO) logic 50 that includes one or more buffers 54(first-in-first out (FIFO) buffers, for example) to receive incomingdata from the core logic 22 (see FIG. 1), which is to be transmitted tothe memory 30. The HSIO logic 50 may also include one or more buffers 55(FIFO buffers, for example) to store an associated clock signal fromcore logic 22. In accordance with some embodiments of the invention, theHSIO logic 50 is clocked by a clock signal (called “HSIO_Clk”), which issource synchronous with the core logic 22. The HSIO logic 50 providesthe stored clock and data signals to a module 60, which generatesexternal data and clock signals on the pads that are connected to thetraces of the memory bus 24. As described further below, the module 60synchronizes the output pad clock signal (provided to the memory bus 24)and its internal clock signals to an output clock signal (called“SS_Clock”) of the HSIO logic 50. In this manner, the HSIO logic 50 usesthe SS_Clock clock signal to clock the outgoing data from the buffers 54and 55, which is received by the module 60.

It is noted that although a single module 60 is depicted in FIG. 2, thememory interface 23 may include multiple modules 60 in accordance withsome embodiments of the invention.

A set of source synchronous clocks is created, from the core logic 22,through the HSIO 50 and continuing to the components of the module 60,described further below. By using source synchronous clocks, the timingmargin between the core logic 22 and the analog input/output (I/O)circuitry interface, such as the module 60, is significantly improved,as compared to conventional memory interfaces.

The module 60 contains data bit transmitters 80 (one exemplary data bittransmitter 80 being depicted in detail in FIG. 2), each of which isassociated with a data bit line of the memory bus 24 and each of whichreceives an associated set of data bit signals (called “SS_Data [0:3]”)from the HSIO logic 50. Each data bit transmitter 80 generates (via anoutput driver 83) its data bit signal on one of the external data bitpad terminals of the module 60, which is connected to a correspondingdata bit line, or trace, of the memory bus 24. Each of the data bittransmitters 80 also receives the SS_Clock signal from the HSIO logic50.

The module 60 also includes a clock transmitter 84, which has the samegeneral design as the data bit transmitter 80, with like referencenumerals being used to depict similar components. The clock transmitter84 receives clock data (indicative of the clock signal to accompany thedata on the memory bus 24) from the HSIO 50 as well as the SS_Clocksignal. The clock transmitter 84 generates an outgoing clock signal (viathe output driver 83) that appears on the external clock pad terminal,which is connected to a corresponding clock line of the memory bus 24.

In general, each transmitter 80, 84 has a relatively small FIFO 82 (aFIFO having a depth of two, for example), which stores the incoming datafrom the HSIO logic 50. As described below, clock signals that controlthe communication of data from the FIFOs 82 to the memory bus 24 areadjusted for purposes of de-skewing; synchronizing the module 60 to theHSIO logic 50 and core logic 22; and compensating for such globalfactors as temperature and voltage drift.

As described further below, the module 60 includes a locked loop circuit110 that synchronizes clock signals for the module 60 with the SS_Clksignal (that clocks the HSIO logic 50). More specifically, the lockedloop circuit 110 includes a delay locked loop (DLL) 130 that locks ontoa baseline clock signal (called “IO_Clk”) that is synchronized to theSS_Clk signal (by a phase locked loop (PLL) 150) for purposes ofgenerating transmit clock signals (called “TxClkxx”) that haveprogrammable offsets, or phases. The TxClkxx transmit clock signals, inturn, are received by the data bit 80 and clock 84 transmitters andcontrol the timing of the data retrieved from the FIFOs 82. Atinitialization of the memory interface 23, each of the TxClkxx signalsare synchronized and have the same phase (all of the TxClkxx signals areidentical to the IO_Clk signal, for example). Thus, all of thetransmitters 80 and 84 may be started deterministically. However, asdescribed below, phase offsets are determined for the TxClkxx signalsfor purposes of establishing individual data bit line de-skewing.Additionally, a baseline clock offset, which is applied to all of theTxClkxx signals that are provided to the data bit transmitters 80 forpurposes of the source synchronization, is continually updated toglobally compensate all of the TxClkxx signals for global factors, suchas process variations and temperature and voltage drift.

For purposes of generating the TxClkxx signals, the locked loop circuit110 includes phase interpolators 115 and 120. The phase interpolator 115generates the TxClkxx signal for the clock transmitter 84 based on acode (called a “baseline code” herein) that is received from acontroller 100; and the phase interpolators 120 (one exemplaryinterpolator 120 being depicted in FIG. 2) generates the TxClkxx signals(which may each be different) for the data bit transmitters 80, based oncodes that are received from the controller 100. Thus, each phaseinterpolator 120 is associated with one of the data bit transmitters 80and generates a TxClkxx signal for the associated data bit transmitter80 based on the received code from the controller 100. The DLL 130 ofthe locked loop circuit 110 generates a baseline clock signal that issynchronized to the IO_Clk signal, and the phase interpolator 115 shiftsthe phase of this signal by the amount indicated in the baseline code togenerate the TxClkxx signal for the clock transmitter 84. Likewise, eachphase interpolator 120 shifts the phases of the signal generated by theDLL 130 according to its received code to generate the TxClkxx signalfor its associated data bit transmitter 80.

The controller 100 generates the baseline code for the phaseinterpolator 115 based on a signal that is provided by a phase detector88 of the clock transmitter 84. In this regard, the phase detector 88compares the phases of the SS_Clock signal and its associated TxClkxxsignal and generates a signal (called “PD_out (UP/DN)”) that indicatesthe result of the comparison so that the controller 100 may generate theappropriate baseline codes to maintain synchronization between theseclock signals. The controller 100 generates the code for each data bittransmitters 80 based on the baseline code and on theindividually-determined de-skew adjustment for that transmitter 80.

FIG. 3 generally depicts a technique 200 for generating the codes (whichare used to generate the TxClkxx transmit clock signals) in accordancewith some embodiments of the invention. Referring to FIG. 3 inconjunction with FIGS. 1 and 2, pursuant to the technique 200, theTxClkxx signal that is provided to the clock transmitter 84 is firstlocked to the SS_Clock signal, thereby making the module 60 sourcesynchronous to the HSIO logic 50, pursuant to block 202. To accomplishthis, the controller 100 determines a baseline code, which indicates abaseline phase for the purpose of source synchronization. The controller100 may continually update the baseline code based on the PD_out (UP/DN)signal that is provided by the phase detector 88. This baseline phase isultimately used as a component in the phase offset for each TxClkxxsignal, with each TxClkxx signal for the data bit transmitters 80 beingadditionally adjusted to compensate for skew. For purposes of settingforth an example, assume the baseline code at this point is 40 hex.

Next, pursuant to the technique 200, for each data bit transmitter 80,an optimal setting for the associated TxClkxx signal is determined,pursuant to block 204. In this regard, the controller 100 determines theoffset that establishes an appropriate timing at the external padsbetween the associated data bit signal and the clock signal. This offsetmay be determined via channel training or may be predetermined from thephysical characteristics of the memory interface 23. Continuing theexample above, for data bit zero (as an example), the controller 100 maydetermine that the setting for the corresponding TxClkxx signal is 43hex. For each data bit transmitter 80, the controller 100 determines(block 208) an offset code, which indicates the offset from the baselinephase. For the example of a baseline code of 40 hex and a code of 43 hexfor data bit zero, the offset code is therefore +3 hex.

After the offset codes for the TxClkxx signals that are provided to thedata bit transmitters 80 are determined, the controller 100 thendetermines the final codes for adjusting the TxClkxx signals. In thisregard, the module 60 or possibly another component (in otherembodiments of the invention) stores the offset codes for the TxClkxxsignals. The code that is used to adjust the phase of each TxClkxxsignal is the sum of the baseline code and the offset code. It is notedthat the baseline code may continually change due to such factors astemperature and voltage drift. Therefore, to generate the TxClkxx signalfor each data bit transmitter 80, the locked loop circuit 110continually determines the baseline code (block 212) and adds to it theassociated offset code to generate the final code, pursuant to block214. For the example that is set forth herein, the baseline code maychange from 40 hex (the original value) to 43 hex due to temperatureand/or voltage drift. For this scenario, the code to adjust the TxClkxxsignal for data bit zero is the summation of 43 hex and 3 hex, or 46hex.

Many different embodiments are within the scope of the appended claims.For example, in accordance with some embodiments of the invention, thecircuitry and techniques that are described herein may be applied to ahigh speed data interface other than a memory bus interface.

While the invention has been disclosed with respect to a limited numberof embodiments, those skilled in the art, having the benefit of thisdisclosure, will appreciate numerous modifications and variationstherefrom. It is intended that the appended claims cover all suchmodifications and variations as fall within the true spirit and scope ofthe invention.

1. A method comprising: providing transmitters, each transmitter beingassociated with a data bit line of a bus and each transmitter beingclocked by an associated transmit clock signal; determining a baselineoffset to apply to a base clock signal to synchronize the base clocksignal to a source clock signal of a source that supplies data to thetransmitters; for each transmitter, determining an associated phaseoffset to compensate for an associated skew; and controlling the phaseof each transmit clock signal based on the associated phase offset andthe baseline offset.
 2. The method of claim 1, further comprising:regulating the baseline phase offset to compensate for temperaturedrift.
 3. The method of claim 1, further comprising: regulating thebaseline phase offset to compensate for voltage drift.
 4. The method ofclaim 1, further comprising: initializing the base clock signal and thetransmit clock signals to have the same phase before determination ofthe phase offsets.
 5. The method of claim 1, further comprising:providing the base clock signal to the bus.
 6. An apparatus, comprising:transmitters, each transmitter being associated with a data bit line ofa bus and each transmitter being clocked by an associated transmit clocksignal; and a circuit to: determine a baseline offset to apply to a baseclock signal to synchronize the base clock signal to a source clocksignal of a source that supplies data to the transmitters, for eachtransmitter, determine an associated phase offset to compensate for anassociated skew, and control the phase of each transmit clock signalbased on the associated phase offset and the baseline offset.
 7. Theapparatus of claim 6, wherein the apparatus comprises a memory interfaceof a memory controller hub.
 8. The apparatus of claim 6, wherein thecircuit regulates the baseline phase offset to compensate fortemperature drift.
 9. The apparatus of claim 6, wherein the circuitregulates the baseline phase offset to compensate for voltage drift. 10.The apparatus of claim 6, wherein each transmitter comprises a FIFO. 11.The apparatus of claim 6, wherein the circuit initializes the base andclock signals to have the same phase before determining the phaseoffsets.
 12. The apparatus of claim 6, further comprising: a clocktransmitter to provide the base clock signal to the bus.